PIC12F1612 | ||||
---|---|---|---|---|
CONFIG1 (address:0x8007, mask:0xFFFF) | ||||
FOSC -- Oscillator Selection Bits | ||||
FOSC = INTOSC | 0xFFFC | INTOSC oscillator: I/O function on CLKIN pin. | ||
FOSC = ECL | 0xFFFD | ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins. | ||
FOSC = ECM | 0xFFFE | ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins. | ||
FOSC = ECH | 0xFFFF | ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins. | ||
PWRTE -- Power-up Timer Enable | ||||
PWRTE = ON | 0xFFDF | PWRT enabled. | ||
PWRTE = OFF | 0xFFFF | PWRT disabled. | ||
MCLRE -- MCLR Pin Function Select | ||||
MCLRE = OFF | 0xFFBF | MCLR/VPP pin function is digital input. | ||
MCLRE = ON | 0xFFFF | MCLR/VPP pin function is MCLR. | ||
CP -- Flash Program Memory Code Protection | ||||
CP = ON | 0xFF7F | Program memory code protection is enabled. | ||
CP = OFF | 0xFFFF | Program memory code protection is disabled. | ||
BOREN -- Brown-out Reset Enable | ||||
BOREN = OFF | 0xF9FF | Brown-out Reset disabled. | ||
BOREN = SBODEN | 0xFBFF | Brown-out Reset controlled by the SBOREN bit in the BORCON register. | ||
BOREN = NSLEEP | 0xFDFF | Brown-out Reset enabled while running and disabled in Sleep. | ||
BOREN = ON | 0xFFFF | Brown-out Reset enabled. | ||
CLKOUTEN -- Clock Out Enable | ||||
CLKOUTEN = ON | 0xF7FF | CLKOUT function is enabled on the CLKOUT pin. | ||
CLKOUTEN = OFF | 0xFFFF | CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin. | ||
CONFIG2 (address:0x8008, mask:0xFFFF) | ||||
WRT -- Flash Memory Self-Write Protection | ||||
WRT = ALL | 0xFFFC | 000h to 1FFFh write protected, no addresses may be modified by EECON control. | ||
WRT = HALF | 0xFFFD | 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control. | ||
WRT = BOOT | 0xFFFE | 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control. | ||
WRT = OFF | 0xFFFF | Write protection off. | ||
ZCDDIS -- Zero Cross Detect Disable Bit | ||||
ZCDDIS = OFF | 0xFF7F | ZCD always enabled. | ||
ZCDDIS = ON | 0xFFFF | ZCD disable. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON. | ||
PLLEN -- PLL Enable Bit | ||||
PLLEN = OFF | 0xFEFF | 4x PLL is enabled when software sets the SPLLEN bit. | ||
PLLEN = ON | 0xFFFF | 4x PLL is always enabled. | ||
STVREN -- Stack Overflow/Underflow Reset Enable | ||||
STVREN = OFF | 0xFDFF | Stack Overflow or Underflow will not cause a Reset. | ||
STVREN = ON | 0xFFFF | Stack Overflow or Underflow will cause a Reset. | ||
BORV -- Brown-out Reset Voltage Selection | ||||
BORV = HI | 0xFBFF | Brown-out Reset Voltage (Vbor), high trip point selected. | ||
BORV = LO | 0xFFFF | Brown-out Reset Voltage (Vbor), low trip point selected. | ||
LPBOR -- Low-Power Brown Out Reset | ||||
LPBOR = ON | 0xF7FF | Low-Power BOR is enabled. | ||
LPBOR = OFF | 0xFFFF | Low-Power BOR is disabled. | ||
LVP -- Low-Voltage Programming Enable | ||||
LVP = OFF | 0xDFFF | High-voltage on MCLR/VPP must be used for programming. | ||
LVP = ON | 0xFFFF | Low-voltage programming enabled. | ||
CONFIG3 (address:0x8009, mask:0xFFFF) | ||||
WDTCPS -- WDT Period Select | ||||
WDTCPS = WDTCPS0 | 0xFFE0 | 1:32 (1 ms period). | ||
WDTCPS = WDTCPS1 | 0xFFE1 | 1:64 (2 ms period). | ||
WDTCPS = WDTCPS2 | 0xFFE2 | 1:128 (4 ms period). | ||
WDTCPS = WDTCPS3 | 0xFFE3 | 1:256 (8 ms period). | ||
WDTCPS = WDTCPS4 | 0xFFE4 | 1:512 (16 ms period). | ||
WDTCPS = WDTCPS5 | 0xFFE5 | 1:1024 (32 ms period). | ||
WDTCPS = WDTCPS6 | 0xFFE6 | 1:2048 (64 ms period). | ||
WDTCPS = WDTCPS7 | 0xFFE7 | 1:4096 (128 ms period). | ||
WDTCPS = WDTCPS8 | 0xFFE8 | 1:8192 (256 ms period). | ||
WDTCPS = WDTCPS9 | 0xFFE9 | 1:16384 (512 ms period). | ||
WDTCPS = WDTCPSA | 0xFFEA | 1:32768 (1 s period). | ||
WDTCPS = WDTCPSB | 0xFFEB | 1:65536 (2 s period). | ||
WDTCPS = WDTCPSC | 0xFFEC | 1:131072 (4 s period). | ||
WDTCPS = WDTCPSD | 0xFFED | 1:262144 (8 s period). | ||
WDTCPS = WDTCPSE | 0xFFEE | 1:524299 (16 s period). | ||
WDTCPS = WDTCPSF | 0xFFEF | 1:1048576 (32 s period). | ||
WDTCPS = WDTCPS10 | 0xFFF0 | 1:2097152 (64 s period). | ||
WDTCPS = WDTCPS11 | 0xFFF1 | 1:4194304 (128 s period). | ||
WDTCPS = WDTCPS12 | 0xFFF2 | 1:8388608 (256 s period). | ||
WDTCPS = WDTCPS1F | 0xFFFF | Software Control (WDTPS). | ||
WDTE -- Watchdog Timer Enable | ||||
WDTE = OFF | 0xFF9F | WDT disabled. | ||
WDTE = SWDTEN | 0xFFBF | WDT controlled by the SWDTEN bit in the WDTCON register. | ||
WDTE = NSLEEP | 0xFFDF | WDT enabled while running and disabled in Sleep. | ||
WDTE = ON | 0xFFFF | WDT enabled. | ||
WDTCWS -- WDT Window Select | ||||
WDTCWS = WDTCWS125 | 0xF8FF | 12.5 percent window open time. | ||
WDTCWS = WDTCWS25 | 0xF9FF | 25 percent window open time. | ||
WDTCWS = WDTCWS375 | 0xFAFF | 37.5 percent window open time. | ||
WDTCWS = WDTCWS50 | 0xFBFF | 50 percent window open time. | ||
WDTCWS = WDTCWS625 | 0xFCFF | 62.5 percent window open time. | ||
WDTCWS = WDTCWS75 | 0xFDFF | 75 percent window open time. | ||
WDTCWS = WDTCWS100 | 0xFEFF | 100 percent window open time (Legacy WDT) . | ||
WDTCWS = WDTCWSSW | 0xFFFF | Software WDT window size control (WDTWS bits). | ||
WDTCCS -- WDT Input Clock Selector | ||||
WDTCCS = LFINTOSC | 0xC7FF | 31.0 kHz LFINTOSC. | ||
WDTCCS = MFINTOSC | 0xCFFF | 31.25 kHz HFINTOSC (MFINTOSC). | ||
WDTCCS = SWC | 0xFFFF | Software control, controlled by WDTCS bits. |
This page generated automatically by the device-help.pl program (2014-05-17 13:45:43 UTC) from the 8bit_device.info file (rev: 1.19) of mpasmx and from the gputils source package (rev: svn 1017). The mpasmx is included in the MPLAB X.