# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck %s -strict-whitespace --check-prefix=GFX12
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding < %s | FileCheck %s -strict-whitespace --check-prefix=GFX12

# Test that VOPD instructions with v_dual_mov_b32 tolerate non-zero bits in
# the unused vsrc1 field.

# v_dual_mov_b32 v255, -1 :: v_dual_fmac_f32 v6, src_scc, v4
# With non-zero vsrc1X=0x42
0xc1,0x84,0x00,0xca,0xfd,0x08,0x06,0xff
# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_fmac_f32 v6, src_scc, v4 ; encoding: [0xc1,0x00,0x00,0xca,0xfd,0x08,0x06,0xff]

# v_dual_add_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc
# With non-zero vsrc1Y=0x42
0xc1,0x08,0x10,0xc9,0xfd,0x84,0x06,0xff
# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0x08,0x10,0xc9,0xfd,0x00,0x06,0xff]

# v_dual_mov_b32 v255, -1 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255
# With non-zero vsrc1X=0x42
0xc1,0x84,0x04,0xca,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255 ; encoding: [0xc1,0x00,0x04,0xca,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]

# v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_mov_b32 v6, src_scc
# With non-zero vsrc1Y=0x42
0xc1,0xfe,0x91,0xc8,0xfd,0x84,0x06,0xff,0x56,0x34,0x12,0xaf
# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0xfe,0x91,0xc8,0xfd,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
